Overview

The RTL8309SB is a 128-pin, ultra-low-power, high-performance 8-port Fast Ethernet single-chip switch with  one  extra  MII  port  for  specific  applications.  It  integrates  all  the  functions  of  a  high  speed  switch  system—including  SRAM  for  packet  buffering,  non-blocking  switch  fabric,  address  management,  one  general use MII interface, eight 10/100Base-TX transceivers, and nine Media Access Controllers—into a single  0.18μm  CMOS  device.  It  provides  compatibility  with  all  industry  standard  Ethernet  and  Fast  Ethernet devices. Only a 25MHz crystal is required; the EEPROM is optional to save BOM costs. The  embedded  packet  storage  SRAM  in  the  RTL8309SB  features superior  memory  management  technology  to  efficiently  utilize  the  memory  space.  An  integrated  1024-entry  look-up  table  stores  MAC  address  and  associated  information  in  a  10-bit  direct  mapping  scheme.  The  table  provides  read/write  access from the SMI interface, and each of the entries can be configured as a static entry. A static entry indicates  that  this  entry  is  controlled  by  the  external  management  processor  and  automatic  aging  and  learning of the entry will not take place. To prevent MAC address mapping collisions, the embedded 16-entry Content-Addressable Memory (CAM) offers another memory space for recording the MAC address when  the  mapped  entry  in  the  lookup  table  is  occupied.  For  each  incoming  packet,  the  RTL8309SB  searches the entries in the lookup table and the 16-entry CAM simultaneously. Then it obtains the correct destination port information to determine which output port the packet should be forwarded to. The aging time  of  the  RTL8309SB  is  around  300  seconds  (this  may  be  sped  up  to  800μs  via  EEPROM  configuration). The ninth port of the RTL8309SB implements a MAC module without a PHY transceiver to provide an MII  interface  for  connection  with  an  external  PHY  or  MAC  in  specific  applications.  This  MII  interface  may  be  set  to  MII  PHY  mode,  SNI  PHY  mode,  or  MII MAC mode to work with an external MAC module in a routing engine application, PHY module in a HomePNA application, or other physical layer transceivers. In  order  to  operate  correctly,  both  sides  of  the  connection  must  be  configured  to  the  same  speed, duplex, and flow control settings. Four pins are used for the ninth port to force the link status. This interface should be 2.5V or 3.3V compatible depending on the voltage supplied to the power pin VDDIO of this interface. The RTL8309SB is capable of preventing broadcast storms  by  setting  strapping  pins  upon  system  reset.  When  this  function  is  enabled,  it  will  drop  broadcast  packets  after  receiving  64  continuous  broadcast  packets. This counter will be reset to 0 every 800ms or when the RTL8309SB receives a non-broadcast packet. The  RTL8309SB  displays  the  port  status  via  fourLED  indicators  (with  optional  blinking  time  setting).  These LEDs blink for diagnostic purposes at system reset time. The RTL8309SB provides various type of RTL8309SB Datasheet Single-Chip 9-Port 10/100Mbps Switch Controller 2 Track ID: JATR-1076-21   Rev. 1.6LED  combinations  to  fit  different  applications.  Eight  combinations  of  link,  activity,  speed,  duplex,  and  collision, are available. Bi-color LED mode is also supported on the Link/Act LED. The RTL8309SB supports standard 802.3x flow control frames for full duplex, and optional backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet buffers and transmitting queues. If one of the forwarding ports is blocked,  or  system  resources  are  unavailable,  broadcast  frames  will  be  dropped  according  to  the  system  configuration. The RTL8309SB support two types of dropping methods. The input dropping method will not  forward  broadcast  packets  to  any  output  ports  and  will  drop  these  packets  directly.  The  output  dropping methodwill forward broadcast packets to non-blocked ports only.  To  improve  real-time  and  multimedia  networking  applications,  the  RTL8309SB  supports  four  types  of  QoS (Quality of Service). These are based on (1) Port-based priority, (2) 802.1p/Q VLAN priority tag, (3) TOS  field  in  IPv4  header,  (4)  Specific  IP  address.  Each  output  port  supports  a  weighted  ratio  of  high-priority and low-priority queues to fit bandwidth requirements in different applications.  The  RTL8309SB  provides  802.1Q  port-based  VLAN  operation  to  separate  logical  connectivity  from  physical connectivity. Each port may be set to any topology via EEPROM upon reset or SMI after reset. The  RTL8309SB  also  provides  options  to  meet  special  application  requirements.  The  first  option  is  the  ARP  VLAN  function,  which  is  used  to  select  to  broadcast  ARP  frames  to  all  VLANs  or  only  forward  ARP frames to the originating VLAN. The second option is the Leaky VLAN function, which is used to select  to  send  unicast  frames  to  other  VLANs  or  only  forward  unicast  frames  to  the  originating  VLAN.  The VLAN tags can be inserted or removed on a per-port basis. In  router  applications,  the  router  may  want  to  know  which  input  port  this  packet  came  from.  The  RTL8309SB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. In this function, the VID information carried in the VLAN tag will be changed to PVID. The RTL8309SB also provides an option to admit VLAN tagged packet with a specific PVID only. If this function is enabled, it will drop non-tagged packets and packets with an incorrect PVID. Each  physical  layer  channel  consists  of  a  4B5B  encoder/decoder,  Manchester  encoder/decoder,  transmit  output driver, scrambler/descrambler, output wave shaping, filters, digital adaptive equalizer, PLL circuit, and  DC  restoration  circuit  for  clock/data  recovery.  This  integrated  chip  benefits  from  low  power  consumption  and  offersadvanced  functions  with  flexible  configuration  for  a  small  workgroup  switch,  multimedia, or real-time traffic mixed with other data type traffic, and other applications. 

Features

• Integrates  eight  10/100  transceivers  and  nine  MAC units for 10Base-T and 100Base-TX. „
• Embedded SRAM for packet storage. „
• On-chip 1024-entry look-up table in direct mapping mode. „
• Embedded 16-entry CAM for hash collision mapping. „
• Provides read/write access to look-up table entries via SMI interface.
• „Provides  non-blocking  wire  speed  reception  and transmission.
• „Flow control fully supported:  ‹
  • Half-duplex: backpressure flow control.
  • ‹Full-duplex: IEEE 802.3x flow control.
• „Support for 4 LEDs per-port in various combinations for comprehensive applications. „Optional loop detection function with an LED to indicate the existence of a loop.
• „LEDs blink upon reset for LED diagnostics.
• „Flexible system configuration by strapping pins, EEPROM, or SMI interface. „
• Optional crossover detection and auto correction for plug-and-play. „
• Fully compliant with IEEE 802.3/802.3u. „Optional Forwarding/Filtering reserved control frames (DID= 0180C2000003~0180C200000F).
• „Optional Broadcast Input/Output Drop flow control. „
• Optional maximum packet length 1536/1552 Bytes. „
• Supports two Power Reduction methods:
  • ‹Power saving mode (automatic cable detection).
  • ‹Power down mode (via PHY register 0.11). „
• Supports QoS function: 
  • ‹QoS based on: (1) Port-based priority (2) 802.1p VLAN tag (3) DiffServ/TOS field in TCP/IP header (4) IP address.
  • ‹Supports two-level priority queues with various weighting ratios.
  • ‹ Queue service rate based on weighted round robin algorithm. ‹
  • Optional auto turn off Flow Control for 1~2 sec to avoid head-of-line blocking.
• „Supports MII interface connection to external MAC or PHY via 3 modes.
  • ‹PHY mode MII for router applications. ‹
  • PHY mode SNI for router applications.
  • ‹MAC mode MII for HomePNA or other PHY applications.
• „Flexible 802.1Q port/tag-based VLAN.  ‹
  • Optional 802.1Q tag-VID aware function. ‹
  • Optional VLAN Ingress Tag Admit Control. ‹
  • Optional VLAN Ingress Member set filtering.
  • ‹Optional ARP VLAN for broadcast packet.
  • ‹Optional Leaky VLAN for unicast packet.
• „Optional 802.1P/Q tag insertion or removal on per-port basis (egress). „
• 25MHz crystal input. „0.18μm, CMOS technology. „
• 128-pin PQFP package. „1.8V core voltage. „
• Independent power options for 2.5V or 3.3V MII interface.